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w78c438c 8-bit microcontroller publication release date: july 1998 - 1 - revision a1 general description the w78c438c is a high-performance single-chip cmos 8-bit microcontroller that is a derivative of the w78c58 microcontroller family. the w78c438c is functionally compatible with the w78c32, except that it provides either a 64 kb program/1 mb data memory address or memory-mapped chip select logic, five general i/o ports, and four external interrupts. in the w78c32, two i/o ports, port 1 and port 3, are available for general-purpose use (port 3 also supports alternative functions), and port 2 and port 0 are used as the address bus and data bus, respectively. to enable port 0 and port 2 to also be used as general purpose i/o ports, the w78c438c provides two dedicated address ports (ap5 and ap6) that serve as address output for 64 kb of memory and one address/data port (dp4) that serves as rom code input and external ram data input/output. unlike the w78c32, this product does not require an external latch device for multiplexing low byte addresses. the w78c438c also provides four pins (ap7.0 ? ap7.3) to support either 64 kb program/1 mb data memory space or memory-mapped chip select logic, one parallel i/o port (port 8) without bit addressing mode, and two additional external interrupts ( int2 , int3 ) . the w78c438c is programmed in a manner fully compatible with that used to program the w78c32, except that the external data ram is accessed by the "movx @ri" instruction. address paging is performed by loading page addresses into the hb (high byte) register, which is not a standard register in the w78c32, before execution of the "movx @ri" instruction. features ? 8-bit cmos microcontroller ? fully static design ? dc to 40 mhz operation ? rom-less operation ? 256-byte on-chip scratchpad ram ? either 64 kb program/1 mb data memory address space or 4 memory-mapped chip select pins ? one 8-bit data/address port ? two 8-bit and one 4-bit (optional) address ports ? five 8-bit bidirectional i/o ports ? four 8-bit bit-addressable i/o ports and one 8-bit parallel i/o port ? eight-source, two-level interrupt capability ? three 16-bit timer/counters ? four external interrupts ? one full-duplex serial channel ? built-in power management ? idle mode ? power-down mode ? packages: ? 84-pin plcc: w78c438cp-24/40 ? 100-pin pqfp: w78c438cf-24/40
w78c438c - 2 - pin configurations 12 13 14 15 16 17 18 19 20 21 22 23 24 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 60 61 62 63 64 25 26 27 28 29 30 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 65 66 67 68 69 70 71 72 73 74 0 1 8 9 1 1 w78c438cp int3 p1.5 p1.6 p1.7 reset p8.1 p8.0 p8.2 p8.4 p8.5 p8.3 p8.6 p8.7 int2 rxd, p3.0 vdd txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 p 2 . 2 32 31 5 6 7 1 2 3 4 8 4 8 0 8 1 8 2 8 3 7 6 7 7 7 8 7 9 p 0 . 0 p 0 . 1 p 0 . 2 p 0 . 3 d p 4 . 1 d p 4 . 0 n c v d d n c d p 4 . 2 d p 4 . 3 d p 4 . 4 d p 4 . 5 d p 4 . 6 d p 4 . 7 p 1 . 0 p 1 . 1 p 1 . 2 p 1 . 3 p 1 . 4 p 0 . 4 7 5 5 1 59 58 57 55 56 54 5 2 5 3 p 3 . 7 , / r d x t a l 2 x t a l 1 v s s a p 7 . 3 , / c s 3 a p 7 . 2 , / c s 2 n c a p 7 . 0 , / c s 0 a p 7 . 1 , / c s 1 a p 6 . 7 a p 6 . 6 a p 6 . 5 a p 6 . 4 a p 6 . 3 a p 6 . 2 a p 6 . 1 a p 6 . 0 p 2 . 0 p 2 . 1 p 3 . 6 , / w r p2.4 p2.5 p2.6 p2.7 ea psen ale ap5.7 ap5.6 ap5.5 ap5.4 ap5.3 ap5.2 ap5.1 v p2.3 ap5.0 p0.7 p0.6 p0.5 v 84-pin plcc dd ss
w78c438c publication release date: july 1998 - 3 - revision a1 pin configurations, continued 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 18 19 9 20 21 22 23 24 0 12 333 345 333 6 3 78 33 90 4 0 25 26 27 28 29 30 4 123 45 6 78 9 444444445 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 9 7 8 9 0 1 2 3 4 5 6 7 8651 2 3 4 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 1 0 v d d n c p 0 . 3 p 0 . 1 p 0 . 2 p 0 . 0 d p 4 . 0 d p 4 . 1 d p 4 . 2 d p 4 . 3 d p 4 . 4 d p 4 . 5 d p 4 . 6 d p 4 . 7 t 2 , p 1 . 0 p 1 . 2 p 1 . 3 p 1 . 4 n c nc nc nc nc p2.4 p2.5 p2.7 p2.6 v ap5.7 ap5.6 ap5.5 ap5.4 ale ap5.0 psen ap5.1 p0.6 p0.5 p0.4 nc nc nc p0.7 ea p2.3 ap5.3 ap5.2 nc v w78c438cf x t a l 2 x t a l 1 v s s n c p 3 . 7 , / r d a p 7 . 3 , / c s 3 a p 7 . 2 , / c s 2 a p 7 . 1 , / c s 1 a p 6 . 7 a p 6 . 2 a p 6 . 1 a p 6 . 4 a p 6 . 6 a p 6 . 3 a p 6 . 5 a p 6 . 0 p 2 . 0 p 2 . 1 p 2 . 2 a p 7 . 0 , / c s 0 nc nc nc nc nc p1.7 nc nc nc p1.5 p1.6 p8.0 reset p8.1 p8.2 p8.3 p8.4 p8.5 p8.7 p8.6 vdd rxd, p3.0 txd, p3.1 t0, p3.4 t1, p3.5 wr, p3.6 int2 int3 int1, p3.3 int0, p3.2 t 2 e x , p 1 . 1 100-pin pqfp dd ss
w78c438c - 4 - pin description p0.0 ? p0.7 i/o port 0 these pins function the same as those in the w78c32, except that a multiplexed address/data bus is not provided during accesses to external memory. p1.0 ? p1.7 i/o port 1 functions are the same as in the w78c32. p2.0 ? p2.7 i/o port 2 functions are the same as in the w78c32, except that an upper address bus is not provided during accesses to external memory. p3.0 ? p3.7 i/o port 3 functions are the same as in the w78c32. dp4.0 ? dp4.7 data/address bus dp4 provides multiplexed low-byte address/data during access to external memory. ap5.0 ? ap5.7 address bus ap5 outputs the <7:0> address of the external rom multiplexed with the <7:0> address of the external data ram. ap6.0 ? ap6.7 address bus ap6 outputs the <15:8> address of the external rom multiplexed with the <15:8> address of the external data ram. during the execution of "movx @ri," the output of ap6 comes from the hb register, which is the page register for the high byte address, and its address is 0a1h. ap7.0 ? ap7.3 address bus/chip select pins set bit 7 of the epma (extended program memory address) register to determine the functions of port 7. when this bit is "0" (default value), ap7 allows the external memory data to be accessed by outputting the <19:16> address of the external memory from bits<3:0> of the epma register during the execution of "movc a, @a+dptr" or "movx dest, src." at all other times, ap7<3:0> will output 0h. when this bit is "1," ap7<3:0> (cs3 ? 0) are the chip select pins, which support memory-mapped peripheral device select, and only one pin is active low at any one time. these pins are decoded by ap6<7:6>. for details, see the table below. ap6.7 ap6.6 description 0 0 ap70: low; others: high 0 1 ap71: low; others: high 1 0 ap72: low; others: high 1 1 ap73: low; others: high
w78c438c publication release date: july 1998 - 5 - revision a1 p8.0 ? p8.7 i/o port functions are the same as those of port 1 in the w78c31, except that they are mapped by the p8 register and not bit-addressable. the p8 register is not a standard register in the w78c32. its address is at 0a6h. int2 , int3 external interrupt, input functions are similar to those of external int0 , int1 in the w78c32, except that the functions/status of these interrupts are determined/shown by the bits in the xicon (external interrupt control) register. the xicon register is bit-addressable but is not a standard register in the w78c32. its address is at 0c0h. for details, see the functional description below. ea external address, input functions same as w78c32. rst, xtal1, xtal2, psen , ale functions same as w78c32. block diagram sfr ram 256 bytes cpu serial port data bus core interrupt int0 timer0 timer2 port 0 port 1 port 2 alternate port 8 dp4 ap5 ap6 ap7 alternate int1 timer1 int2 int3 port 3 alternate
w78c438c - 6 - functional description the w78c438c is a functional extension of the w78c58 microcontroller. it contains a 256 8 ram, 64 kb program/1 mb data memory address or memory-mapped chip select logic, two 8-bit address ports, one 8-bit data port, five general i/o ports, four external interrupts, three timers/counters, and one serial port. dedicated data and address port the w78c438c provides four general-purpose i/o ports for w78c32 applications; the address and data bus are separated from port 0 and port 2 so that these ports can be used as general-purpose i/o ports. in this product, dp4 is the data bus for external rom and ram, ap5<7:0> are the low byte address, ap6<7:0> are the high byte address, psen enables the external rom to dp4, and p3.6 ( wr ) and p3.7 ( rd ) are the write/read control signals for the external ram. the external latch for multiplexing the low byte address is no longer needed in this product. the w78c438c uses ap5 and ap6 to support 64 kb external program memory and 64 kb external data memory, just as a standard w78c32 does. the w78c438c provides four pins, ap7.3 ? ap7.0 (cs3 ? cs0), to support either 64 kb program/1 mb data memory space or memory-mapped chip select logic. bit 7 of the epma (extended program memory address) register, which is described in table 1 below, determines the functions of these pins. when this bit is "0" (the default value), ap7<3:0> support external program/data memory addresses up to 64 kb/1 mb for applications which need additional external memory to store large amounts of data. although there is 1m bytes memory space, instructions stored here can not be run at full range of this area except the first 64 kbytes. it is owing to the fact that during the instruction fetch cycle, ap7<3:0> always output 0s to address lines a19 ? a16. this limits the program code to store at address 0 ? 0ffffh (64k). the rest of the area (10000h ? fffffh) can be treated as rom data storage which can be read by "movc a, @a+dptr" instruction. when "movc a, @a+dptr" is executed to read the external rom data or "movx dest, src" is executed to access the external ram data, ap7<3:0> output address <19:16> from bits <3:0> of the epma (extended program memory address) register. at other times, ap7<3:0> always output 0h to ensure the instruction fetch is within the 64k program memory address. different banks can be selected by modifying the content of the epma register before the execution of "movc a, @a+dptr" or "movx dest, src." [example]. access the external rom/ram data from external memory space. clr a ; clear accumulator. mov dptr, #0h ; clear dptr. mov 0a2h, #02 ; initialize epma(0a2h). epma.7 = 0: extended memory space ; epma.<3:0> = 0010b, the address range: 20000 ? 2ffffh. movc a, @a+dptr ; read the external rom data from location 20000h. movx a, @dptr ; read the external ram data from location 20000h. clr a mov 0a2h, #03h ; epma.<3:0> = 0011b, the address range: 30000h ? 3ffffh. movc a, @a+dptr ; read the external rom data from location 30000h. movx @dptr, a ; write the contents of accumulator to external ram data. ; location 30000h.
w78c438c publication release date: july 1998 - 7 - revision a1 (a) epma.7 = 0 w78c438 eprom ram ap5 psen addr 1mb (20-bit) addr (20-bit) data ap6 dp4 wr rd p3 oe we oe ap7 p1 p0 p2 p8 int1 int3 int0 int2 \ 8 \ 4 \ 8 \ 8 64k program data area when bit 7 of the epma is "1," ap7<3:0> are the output pins that support memory-mapped peripheral chip select logic, which eliminates the need for glue logic. these pins are decoded by ap6<7:6>. only one pin is active low at any time. that is, they are active individually with 16k address resolution. for example, cs0 is active low in the address range from 0000h to 3fffh, cs1 is active low in the address range from 4000h to 7fffh, and so forth. (b) epma.7 = 1 w78c438 ap5 psen ap6 dp4 wr rd p3 p1 p0 p2 p8 int1 int3 int0 int2 ram addr (14-bit) data we oe ap7.0 ap7.1 ap7.2 ap7.3 0000h 3fffh 4000h 7fffh 8000h bfffh c000h ffffh \ 8 \ 8 \ 6 \ 8 \ 8 device device device (16k) (16k) (16k) (16k) eprom oe 64k program data area addr (16-bit)
w78c438c - 8 - the epma register is a nonstandard 8-bit sfr at address 0a2h in the standard w78c32. to read/write the epma register, one can use the "mov direct" instruction or "read-modify-write" instructions. bits <6:4> of the epma register are reserved bits, and their output values are 111b if they are read. the content of epma is 70h after a reset. the epma register does not support bit- addressable instructions. bit name function 7 epma7 epma7 = 0: 64 kb program/1 mb data memory space mode epma7 = 1: memory-mapped chip select mode 6 epma6 reserved 5 epma5 reserved 4 epma4 reserved 3 epma3 value of ap7.3 2 epma2 value of ap7.2 1 epma1 value of ap7.1 0 epma0 value of ap7.0 table 1. functional description of epma register additional i/o port the w78c438c provides one parallel i/o port, port 8. its function is the same as that of port 1 in the w78c31, except that it is mapped by the p8 register and is not bit-addressable. the p8 register is not a standard register in the standard w78c32. its address is at 0a6h. to read/write the p8 register, one can use the "mov direct" instruction or "read-modify-write" instructions. [example]: mov 0a6h, a ; output data via port 8. mov a, 0a6h ; input data via port 8. additional external interrupt the w78c438c provides two additional external interrupts, int2 and int3 , whose functions are similar to those of external interrupts 0 and 1 in the w78c32. the functions (or the status) of these interrupts are determined by (or shown by) the bits in the xicon (external interrupt control) register. for details, see table 2. the xicon register is bit-addressable but is not a standard register in the standard 80c32. its address is at 0c0h. to set/clear the bit of the xicon register, one can use the "setb( clr) bit" instruction. for example, "setb 0c2h" sets the ex2 bit of xicon. the interrupt vector addresses and the priority polling sequence within the same level are shown in table 3. [example]. setb 0c0h ; int2 is falling-edge triggered. setb 0c3h ; int2 is high-priority. setb 0c2h ; enable int2 . clr 0c4h ; int3 is low-level triggered.
w78c438c publication release date: july 1998 - 9 - revision a1 bit addr. name function 7 0c7h px3 high/low priority level for int3 is specified when this bit is set/cleared by software. 6 0c6h ex3 enable/disable interrupt from int3 when this bit is set/cleared by software. 5 0c5h ie3 if it3 is "1," ie3 is set/cleared automatically by hardware when interrupt is detected/serviced. 4 0c4h it3 int3 is falling-edge/low-level triggered when this bit is set/cleared by software. 3 0c3h px2 high/low priority level for int2 is specified when this bit is set/cleared by software. 2 0c2h ex2 enable/disable interrupt from int2 when this bit is set/cleared by software. 1 0c1h ie2 if it2 is "1," ie2 is set/cleared automatically by hardware when interrupt is detected/serviced. 0 0c0h it2 int2 is falling-edge/low-level triggered when this bit is set/cleared by software. table 2. functions of xicon register interrupt source vector address priority sequence external interrupt 0 03h 0 (highest) timer/counter 0 0bh 1 external interrupt 1 13h 2 timer/counter 1 1bh 3 serial port 23h 4 timer/counter 2 2bh 5 external interrupt 2 33h 6 external interrupt 3 3bh 7 (lowest) table 3. priority of interrupts newly added special function registers the w78c438c uses four newly defined special function registers, which are described in table 4. to read/write these registers, use the "mov direct" or "read-modify-write" instructions. register addr. function length r/w type value after reset 1 hb a1h during the execution of "movx @ri," the content of hb is output to ap6. 8 r/w 00h 2 epma a2h epma.7 determines functions of ap7. epma.3 ? epma.0 determine values of ap7<3:0> when epma.7 is "0." 8 r/w 70h 3 p8 a6h the content of p8 is output to port 8. 8 r/w 0ffh 4 xicon c0h the bits of xicon determine/show the functions/status of int2 ? int3 . bit-addressable. 8 r/w 00h table 4. newly added special function registers of the w78c438c
w78c438c - 10 - notes: 1. the instructions used to access these nonstandard registers may cause assembling errors with respect to the 2500 a. d. assembler, but these errors can be ignored by adding directive ".ramchk off" ahead these instructions. 2. in the newly added sfr of w78c438c, only xicon register is bit-addressable. power reduction function the w78c438c supports power reduction just as the w78c32 does. the following table shows the status of the external pins during the idle and power-down modes. function ale, psen p0 ? p3, p8 dp4 ap5, ap6 ap7 idle 1 1 port data floating address note power down 0 0 port data floating address note note: ap7 is either 0 or a value decoded by ap6<7:6>, depending on the value of epma.7. programming difference the w78c438c is programmed in the same way as the w78c32, except that the external data ram is accessed by a "movx @ri" instruction. to support address paging, there is an additional 8-bit sfr "hb" (high byte), which is a nonstandard register, at address 0a1h. during execution of the "movx @ri" instruction, the contents of hb are output to ap6. the page address is modified by loading the hb register with a new value before execution of the "movx @ri" instruction. to read/write the hb register, one can use the "mov direct" instruction or "read-modify-write" instructions. the hb register does not support bit-addressable instructions. [example]. mov r1, #0h ; r1 = 0. mov 0a1h, #0ffh ; hb contents ffh. movx a, @r1 ; read the contents of external ram location ff00h into ; accumulator. mov 0a1h, #12h ; hb contents 12h. movx @r1, a ; copies the contents of accumulator into external ram ; location 1200h. absolute maximum ratings parameter symbol min. max. unit dc power supply v dd ? v ss -0.3 +7.0 v input voltage v in v ss -0.3 v dd +0.3 v operating temperature t opr 070 c storage temperature t stg -55 +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability o f the device.
w78c438c publication release date: july 1998 - 11 - revision a1 dc characteristics v dd ? v ss = 5v 10%, t a = 25 c, f osc = 20 mhz, unless otherwise specified. parameter sym. test conditions min. typ. max. unit oper. voltage v dd 4.5 5 5.5 v oper. current i dd * no load - - 20 ma idle current i idle program idle mode - - 7 ma pwdn current i pwdn program power-down mode - - 50 a input leakage current i lk1 int2 , int3 internal pull-high notes 1, 2 -300 - +10 a input leakage current i lk2 reset internal pull-low notes 1, 2 -10 - +300 a input leakage current i lk3 ea , port 0, dp4 note 1 -10 - +10 a input leakage current i lk4 p1, p2, p3, p8 note 1 -50 - +10 a output low voltage v ol1 i ol1 = 2 ma (port 1, 2, 3, 8) - - 0.45 v output high voltage v oh1 i oh1 = -100 a (port 1, 2, 3, 8) 2.4 - - v output low voltage v ol2 i ol2 = 4ma note 3 (ale, psen, p0, dp4) - - 0.45 v output high voltage v oh2 i oh2 = -400 a note 3 (ale, psen, p0, dp4) 2.4 - - v output low voltage v ol3 i ol2 = 2 ma (ap5, ap6, ap7) - - 0.45 v output high voltage v oh3 i oh2 = -100 a (ap5, ap6, ap7) 2.4 - - v input voltage v ilt v dd = 5v 10% 0 - 0.8 v input voltage v iht v dd = 5v 10% 2.4 - note 4 v input voltage v ilc v dd = 5v 10%, xtal1 note 5 0 - 0.8 v input voltage v ihc v dd = 5v 10%, xtal1 note 5 3.5 - note 4 v input voltage v ilr v dd = 5v 10%, reset note 5 0 - 0.8 v input voltage v ihr v dd = 5v 10%, reset note 5 2.4 - note 4 v notes: 1. 0 < v in < v dd , for int2 , int3 , reset, ea , port 0, dp4, p1, p2, p3 and p8 inputs in leakage. 2. using an internal pull low/high resistor (approx. 30k). 3. ale, psen , p0 and dp4 in external program or data access mode. 4. the maximum input voltage is v dd +0.2v. 5. xtal1 is a cmos input and reset is a schmitt trigger input.
w78c438c - 12 - ac characteristics ac specifications are a function of the particular process used to manufacture the product, the ratings of the i/o buffers, the capacitive load, and the internal routing capacitance. most of the specifications can be expressed in terms of multiple input clock periods (t cp ), and actual parts will usually experience less than a 20 ns variation. clock input waveform parameter symbol min. typ. max. unit notes operating speed f op 0 - 40 mhz 1 clock period t cp 25 - - ns 2 clock high t ch 10 - - ns 3 clock low t cl 10 - - ns 3 notes: 1. the clock may be stopped indefinitely in either state. 2. the t cp specification is used as a reference in other specifications. 3. there are no duty cycle requirements on the xtal1 input. program fetch cycle parameter symbol min. typ. max. unit address valid to psen low t apl 2 t cp --ns psen low to data valid t pdv --2 t cp ns data memory read/write cycle parameter symbol min. typ. max. unit address valid to rd low t arl 4 t cp - 4 t cp + ? ns rd low to data valid t rdv --4 t cp ns data hold after rd high t rdq 0-2 t cp ns rd pulse width t rs 6 t cp - ? 6 t cp -ns address valid to wr low t awl 4 t cp - 4 t cp + ? ns data valid to wr low t dwl 1 t cp --ns data hold after wr high t wdq 1 t cp --ns wr pulse width t ws 6 t cp - ? 6 t cp -ns note: " ? " (due to buffer driving delay and wire loading) is 20 ns.
w78c438c publication release date: july 1998 - 13 - revision a1 timing waveforms program fetch cycle s1 s2 xtal1 psen s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ap6<7:0> ap5<7:0> dp4<7:0> address code address t apl t pdv data memory read/write cycle s1 s2 s3 s8 s9 s10 s11 s12 s4 s5 s6 s7 xtal1 psen data addr. rd dp4<7:0> wr dp4<7:0> data out addr. addr. t rs t arl t rdv t rdq t ws t dwl t wdq t awl ap6<7:0> dph or hb sfr out pgm address pgm address dpl or ri out ap5<7:0> ap7<3:0> addr <19:16> out (when bit7 of epma is 0.)
w78c438c - 14 - typical application circuits using 128k 8 bit external eprom (w27e010) 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 18 19 20 21 22 23 24 25 26 27 28 29 30 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 8 9 7 8 9 0 1 2 3 4 5 6 7 8 9 0 65 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 1 0 p1.5 ap5.7 p 2 . 2 p2.3 p2.4 p0.5 p0.7 p0.6 ap5.6 ap5.5 ap5.4 ap5.3 ap5.2 ap5.1 ap5.0 p2.5 p2.6 p2.7 psen ale ea a p 6 . 7 0 12 333 345 333 6 3 78 33 90 44 12345678 9 444444445 a x t l 1 x t a l 2 5 v 8.2 k 10 u c2 c1 r p1.6 p1.7 reset p8.1 p8.2 p8.3 p8.4 p8.5 p3.0, rxd p3.1, txd p3.3, int1 p3.4, t0 int3 p3.2, int0 p3.5, t1 p3.6, wr int2 p8.0 p8.6 p8.7 a p 7 . 3 , / c s 3 a p 7 . 2 , / c s 2 a p 7 . 1 , / c s 1 a p 7 . 0 , / c s 0 a p 6 . 6 a p 6 . 5 a p 6 . 4 a p 6 . 3 a p 6 . 2 p 3 . 7 , / r d a p 6 . 0 a p 6 . 1 p 2 . 1 p 2 . 0 p0.4 p 1 . 4 p 1 . 3 p 1 . 2 p 1 . 1 p 1 . 0 d p 4 . 7 d p 4 . 6 d p 4 . 5 d p 4 . 4 d p 4 . 3 d p 4 . 2 d p 4 . 1 d p 4 . 0 p 0 . 0 p 0 . 1 p 0 . 2 p 0 . 3 vdd vdd vss w78c438c a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 29 a15 3 ce oe o0 13 o1 14 o2 15 o3 17 o4 18 o5 19 o6 20 o7 21 gnd a16 vpp vcc pgm vss 2 22 24 1 32 31 16 v d d n c n c nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc w27e010 v s s n c figure a
w78c438c publication release date: july 1998 - 15 - revision a1 crystal c1 c2 r 16 mhz 30p 30p ? 24 mhz 15p 15p ? 33 mhz 10p 10p 6.8k 40 mhz 5p 5p 6.8k above table shows the reference values for crystal applications. notes: 1. for c1, c2, r components refer to figure a. 2. it is recommended that the crystals be replaced with oscillators for applications above 35 mhz. package dimensions 84-pin plcc 2 a h d d e b e h e y a a seating plane d g e 11 84 75 1 12 32 33 53 54 74 symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e 0.020 0.143 0.026 0.016 0.006 1.148 1.095 1.180 0.090 0.148 0.028 0.018 0.008 1.153 1.115 1.190 0.100 0.050 0.185 0.153 0.032 0.022 0.012 1.158 1.135 1.200 0.110 0.004 0.51 3.63 0.66 0.41 0.15 29.17 27.81 29.98 2.29 3.76 0.71 0.46 0.20 29.29 28.32 30.23 2.54 1.27 4.70 3.89 0.81 0.56 0.30 29.41 28.83 30.48 2.79 0.10 0.044 0.056 1.12 1.42 29.41 29.29 29.17 1.158 1.153 1.148 28.83 28.32 27.81 1.135 1.115 1.095 0 10 10 0 30.48 30.23 29.98 1.200 1.190 1.180 on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar flash. 1. dimension d & e do not include interlead notes:
w78c438c - 16 - package dimensions, continued 100-pin qfp 51 50 31 30 1 80 81 100 1 a h d d e b e h e y a a seating plane l l 1 see detail f detail f c 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual inspection spec. 0.102 0 12 0 0.004 2.413 1.397 19.10 1.194 18.80 0.991 18.49 0.095 0.055 0.988 0.752 0.047 0.976 0.740 0.039 0.964 0.728 0.65 20.13 14.13 0.254 0.407 2.972 3.30 20.00 14.00 2.845 19.87 13.87 0.101 0.254 2.718 0.10 0.792 0.556 0.010 0.016 0.117 0.130 0.787 0.551 0.112 0.026 0.782 0.546 0.004 0.010 0.107 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.012 0.006 0.152 0.305 24.49 24.80 25.10 12 0.020 0.087 0.032 0.103 0.498 0.802 2.21 2.616 2 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792766 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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